1. Field of the Invention
The present invention relates charge pump circuits, and to integrated circuits using charge pumps to produce on-chip voltages outside the range of the supply potentials.
2. Description of Related Art
Charge pump circuits are used to generate voltages on integrated circuits and elsewhere, which are higher than or more negative than input supply voltages. Charge pump circuits also called voltage booster circuits and voltage level shifting circuits, are becoming more important as low power applications of integrated circuits are designed to work with lower supply potentials. Thus, as integrated circuits work with supply potentials in the range of 2 to 3 volts or lower, and as circuits on the integrated circuits require operating voltages which are on the order of 5 volts or higher, or require operating voltages which are negative, charge pump circuits are becoming more important.
Representative prior art for charge pump circuits, and particularly negative charge pumps, are described in U.S. Pat. No. 5,489,870 entitled VOLTAGE BOOSTER CIRCUIT; U.S. Pat. No. 5,612,921 entitled LOW SUPPLY VOLTAGE NEGATIVE CHARGE PUMP; U.S. Pat. No. 5,502,629 entitled DC-DC CONVERTER; and in Choi, et al., FLOATING-WELL CHARGE PUMP CIRCUITS FOR SUB-2.0 v SINGLE POWER SUPPLY FLASH MEMORY, 1997 Symposium on VLSI Circuits Digest of Technical Papers, pages 61-62, Jun. 12-14, 1997. Also, prior art charge pump circuitry is disclosed in International Patent Application having Publication Number WO 98/16010 entitled TRIPLE WELL CHARGE PUMP which was owned at the time of invention and is currently owned by the same assignee as the present application.
As is disclosed in the International Application WO 98/16010, triple well transistors can be utilized in charge pumps to increase the efficiency. The triple well transistor comprises a MOS transistor which has source and drain regions of one conductivity type such as n-type, a channel well in which the source and drain regions are formed, of the opposite conductivity such as p-type, and an isolation well of the first conductivity type in which the channel well is formed. All of this is established in a substrate having the second conductivity type. The triple well transistor allows for isolation of the pump transistors from the substrate, as well as allowing for biasing of the channel regions of the transistors to reduce the body effect, and therefore reduce the threshold drop across the transistor. By reducing the threshold drop, efficiency of the charge pump is improved because less voltage is lost as the pumped charge is transferred from one stage to the next.
FIG. 1 illustrates a prior art negative charge pump using triple well n-type MOS transistors. In FIG. 1, an input node 10 is clamped to ground through a first triple well n-channel MOS (NMOS) transistor 11. The transistor 11 has its source, gate and channel well coupled to node 10. The source of transistor 11 is connected to ground. The isolation well is coupled to the supply potential VDD. Node 10 is also coupled across a capacitor 12 to a clock signal. A second transistor 13 has its source connected to node 10, and its gate, channel well, and drain coupled to node 14. The isolation well of transistor 13 is also connected to the supply potential VDD. Node 14 is connected through a capacitor 15 to a clock signal which is 180.degree. out of phase with the clock signal applied to capacitor 12. Also, a clamp transistor 16 formed using a triple well NMOS device has its source connected to ground, and its gate, drain and channel well connected to node 14. The isolation well of transistor 16 is connected to the supply potential VDD. Finally, node 14 is connected to the source of a fourth transistor 17. The gate, drain and channel well are coupled to an output terminal 18. The isolation well is coupled to the supply potential VDD. The clock signals are illustrated at traces 19 and 20 in FIG. 1. Basically the transistors 13 and 17 are connected in a diode configuration. The isolation well is connected to VDD, or another potential between zero and the supply to potential to avoid a pn junction turn on between the isolation well and the substrate.
In operation, the node 10 is clamped to a voltage near a threshold above ground. When the clock signal CK on capacitor 12 transits from VDD to ground, node 10 is pushed negative by an amount near the absolute value of VDD. This back biases the clamp transistor 11, allowing node 10 to go negative. As node 10 goes negative, charge is transferred through transistor 13 to node 14. This pulls node 14 to a voltage below the bias point established by transistor 16. On the falling edge of the signal CKB across capacitor 15, node 14 is pushed even further negative, and the charge is transferred across transistor 17 to the output terminal 18.
One problem with a triple well MOS connected transistor of the type shown, is the formation of the parasitic NPN bipolar transistor between the n-diffusion of the source, the channel well which is p-type, and the isolation well which is n-type. In this case, the channel well acts as the base of the NPN transistor. The NPN transistor can turn on if the emitter formed by the source of the NMOS transistor falls to a level more than the NPN threshold less than the base. This causes current flow from the isolation well into the source of the NMOS transistor and decreases pump efficiency.
Thus, the parasitic NPN transistor in the charge transfer transistor 13 may experience a condition in which its emitter (the source of NMOS 13) is biased at a negative voltage after the falling edge of the clock CK while its collector (isolation well at VDD) and base (channel well at node 14) are at higher potentials. In this case, parasitic NPN transistor in the charge transfer device 13 turns on at the same time as or before the NMOS device 13 begins conducting charge from node 10 to node 14.
Accordingly, it is desirable to provide an efficient two phase charge pump, which is compact and suitable for use in integrated circuits in the generation of negative voltages.